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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00647 rev. *f revised march 10, 2016 S70FL256P 256-mbit 3.0v flash this product is not recommended for new and current designs. for new and current designs, the s25fl256s supersedes S70FL256P. t his is the factory-recommended migration path. refer to the s25fl256s datas heet for specifications and ordering information, and an98592 f or changes required to migrate from exis ting designs based on S70FL256P. distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3. 6v read and write operations ? memory architecture ? uniform 64 kb sectors ? top or bottom parameter block (two 64-kb sectors broken down into sixteen 4-kb sub-sectors each) for each flash die ? uniform 256 kb sectors (no 4-kb sub-sectors) ? 256-byte page size ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program operations are on a page by page basis ? accelerated programming mode via 9v w#/acc pin ? quad page programming ? erase ? bulk erase function for each flash die ? sector erase (se) command (d8h) for 64 kb and 256 kb sectors ? sub-sector erase (p4e) command (20h) for 4 kb sectors (for uniform 64-kb sector device only) ? sub-sector erase (p8e) command (40h) for 8 kb sectors (for uniform 64-kb sector device only) ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res command one-byte electronic signature for backward compatibility ? one-time programmable (otp) area on each flash die for permanent, secure identification; can be programmed and locked at the factory or by the customer ? cfi (common flash interface) compliant: allows host system to identify and accomm odate multiple flash devices ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 24-ball bga (6 ? 8 mm) package, 5 ? 5 pin configuration performance characteristics ? speed ? normal read (serial): 40 mhz clock rate ? fast_read (serial): 104 mhz clock rate (maximum) ? dual i/o fast_read: 80 mhz clock rate or 20 mb/s effective data rate ? quad i/o fast_read: 80 mhz clock rate or 40 mb/s effective data rate ? power saving standby mode ? standby mode 160 a (typical) ? deep power-down mode 6 a (typical) memory protection features ? memory protection ? w#/acc pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status register configure pa rts of memory as read-only software features ? spi bus compatible serial interface general description this document contains information for the S70FL256P device, which is a dual die stack of two s25fl129p die. for detailed specifications, refer to the discrete die datasheet. document name cypress document number s25fl129p, 128-mbit 3.0v flash memory datasheet 002-00648 not recommended for new design
document number: 002-00647 rev. *f page 2 of 16 S70FL256P contents 1. block diagram .............................................................. 3 2. connection diagrams .................................................. 4 3. input/output description ............................................. 5 4. logic symbol ............................................................... 5 5. device operations ....................................................... 6 5.1 programming ................................................................. 6 5.2 simultaneous die operation .......................................... 6 5.3 sequential reads........................................................... 6 5.4 sector/bulk erase .......................................................... 6 5.5 status register .............................................................. 6 5.6 configuration register ................................................... 6 5.7 block protection ............................................................. 6 6. read identifi cation (rdid) ........................................... 6 7. dc characteristics ........................................................ 7 8. test conditions ............................................................. 8 9. ac characteristics ........................................................ 9 9.1 capacitance .............. ........................................... ......... 10 10. ordering information .................................................. 11 10.1 valid combinations ....................................................... 11 11. physical dimensions .................................................. 12 11.1 sl3 016 ? 16-pin wide plastic small outline package (300-mil body width) .........................12 11.2 zsa024 ? 24-ball ball grid array (6 8 mm) package ........................................................................13 12. revision history .......................................................... 14 not recommended for new design
document number: 002-00647 rev. *f page 3 of 16 S70FL256P 1. block diagram si/io0 si/io0 w#/acc/io2 w#/acc/io2 so/io1 hold#/io3 hold#/io3 vss vss sck sck cs#1 cs# vcc vcc si/io0 w#/acc/io2 hold#/io3 vss sck cs#2 cs# vcc so/io1 so/io1 fl129p flash memory fl129p flash memory not recommended for new design
document number: 002-00647 rev. *f page 4 of 16 S70FL256P 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) note: dnc = do not connect (reserved for future use) figure 2.2 6 x 8 mm 24-ball bga package, 5 x 5 pin configuration 1 2 3 4 16 15 14 13 hold#/io3 vcc dnc dnc dnc dnc si/io0 sck 5 6 7 8 12 11 10 9 w#/acc/io2 gnd dnc dnc dnc cs2# cs1# so/io1 3 25 4 1 dnc dnc dnc dnc b d e a c gnd sck dnc vcc dnc cs2# cs1# dnc w#/acc/io2 dnc si/io0 so/io1 dnc hold#/io3 dnc dnc dnc dnc dnc dnc not recommended for new design
document number: 002-00647 rev. *f page 5 of 16 S70FL256P 3. input/output description 4. logic symbol signal i/o description so/io1 i/o serial data output : transfers data serially out of the device on the falling edge of sck. functions as an i/o pin in dual and quad i/o, and quad page program modes. si/io0 i/o serial data input : transfers data serially into the device. device latches commands, addresses, and program data on si on the rising edge of sck. functions as an i/o pin in dual and quad i/o mode. sck input serial clock : provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs1# cs2# input chip selects : places one of the flash die in active power mode when driven low. deselects flash die and places so at high impedance when high. after power-up, device requires a falling edge on cs1# and cs2# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold#/io3 i/o hold : pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs1# or cs2# also be driven low. functions as an i/o pin in quad i/o mode. w#/acc/io2 i/o write protect : protects the memory area sp ecified by status register bits bp2:bp0. when driven low, prevents any program or erase command from alte ring the data in the protected memory area. functions as an i/o pin in quad i/o mode. v cc input supply voltage gnd input ground cs1# so/io1 w#/acc/io2 gnd si/io0 sck hold#/io3 v cc cs2# not recommended for new design
document number: 002-00647 rev. *f page 6 of 16 S70FL256P 5. device operations 5.1 programming each flash die must be programmed independentl y due to the nature of the dual die stack. 5.2 simultaneous die operation the user may only access one flash die of the dual di e stack at a time via its respective chip select. 5.3 sequential reads sequential reads are not supported across the end of the first fl ash die to the beginning of the second. if the user desires to sequentially read across the two die, data must be read out of the first die via cs 1# and then read out of the second die via c s2#. 5.4 sector/bulk erase a sector erase command must be issued for sectors in each flas h die separately. full device bulk erase via a single command is not supported due to the nature of the dual die stack. a bulk erase command must be issued for each die. 5.5 status register each flash die of the dual die stack is ma naged by its own status register. reads an d updates to the status registers must be managed separately. it is recommended that status register control bit settings of each die are kept identical to maintain consistency when switching between die. 5.6 configuration register each flash die of the dual die stack is ma naged by its own configuration register. updates to the configuration register contro l bits must be managed separately. it is recommended that configuration register control bit settings of each die are kept identical t o maintain consistency when switching between die. 5.7 block protection each flash die of the dual die stack will maintain its own block protection. updates to the tbprot and bpnv bits of each die mu st be managed separately. by default, each die is configured to be pr otected starting at the top (hig hest address) of each array, but no address range is protected. it is recommended that the block pr otection settings of each die are kept identical to maintain consistency when switching between die. 6. read identification (rdid) the read identification (rdid) command outputs the one-byte manufacturer identification, followed by the two-byte device identification and the bytes for the common flash interface (cfi) tables. each di e of the fl256p dual die stack will have ident ical identification data as the fl129p die, with the exception of the cfi data at byte 27h, as shown in table 6.1 . table 6.1 product group cfi device geometry definition byte data description 27h 19h device size = 2^n byte not recommended for new design
document number: 002-00647 rev. *f page 7 of 16 S70FL256P 7. dc characteristics this section summarizes the dc characteristics of the device. designers should check that the operating conditions in their cir cuit match the measurement conditions specif ied in the test specifications in table 8.1 on page 8 , when relying on the quoted parameters. notes: 1. typical values are at t ai = 25c and v cc = 3v. 2. bulk erase is on a die per die basis, not for the whole device. table 7.1 dc characteristics (cmos compatible) symbol parameter test conditions limits unit min. typ. (1) max. v cc supply voltage ? 2.7 ? 3.6 v v hh acc program acceleration voltage v cc = 2.7v to 3.6v 8.5 ? 9.5 v v il input low voltage ?? 0.3 ? 0.3 x v cc v v ih input high voltage ? 0.7 x v cc ? v cc +0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min. ?? 0.4 v v oh output high voltage i oh = -0.1 ma v cc - 0.6 ? v i li input leakage current v cc = v cc max, v in = v cc or gnd ?? ? 2a i lo output leakage current v cc = v cc max, v in = v cc or gnd ?? ? 2a i cc1 active power supply current - read (so = open) at 80 mhz (dual or quad) ?? 44 ma at 104 mhz (serial) ?? 32 at 40 mhz (serial) ?? 15 i cc2 active power supply current (page program) cs# = v cc ?? 26 ma i cc3 active power supply current (wrr) cs# = v cc ?? 15 ma i cc4 active power supply current (se) cs# = v cc ?? 26 ma i cc5 active power supply current (be) (2) cs# = v cc ?? 26 ma i sb1 standby current cs# = v cc ; so + v in = gnd or v cc ? 160 500 a i pd deep power-down current cs# = v cc ; so + v in = gnd or v cc ? 620a not recommended for new design
document number: 002-00647 rev. *f page 8 of 16 S70FL256P 8. test conditions figure 8.1 ac measurements i/o waveform note: 1. input rise and fall times are 0-100%. table 8.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times (1) 5n s input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input levels input and output timing reference levels 0.5 v cc not recommended for new design
document number: 002-00647 rev. *f page 9 of 16 S70FL256P 9. ac characteristics notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst-case conditions of 85c; v cc = 2.7v; 100,000 cycles. 3. acceleration mode (9v acc) only in program mode, not erase. table 9.1 ac characteristics symbol (notes) parameter (notes) min. (notes) typ (notes) max (notes) unit f r sck clock frequency for read command dc ? 40 mhz sck clock frequency for rdid command dc ? 50 mhz f c sck clock frequency for all others: fast_read, pp, qpp, p4e, p8e, se, be, dp, res, wren, wrdi, rdsr, wrr, read_id dc ? 104 (serial) 80 (dual/quad) mhz t wh , t ch (5) clock high time 4.5 ?? ns t wl , t cl (5) clock low time 4.5 ?? ns t crt , t clch clock rise time (slew rate) 0.1 ?? v/ns t cft , t chcl clock fall time (slew rate) 0.1 ?? v/ns t cs (9) cs# high time (read instructions) cs# high time (program/erase) 10 50 ?? ns t css cs# active setup time (relative to sck) 3 ?? ns t csh cs# active hold time (relative to sck) 3 ?? ns t su:dat data in setup time 3 ?? ns t hd:dat data in hold time 2 ?? ns t v clock low to output valid 0 ? 9 (serial) ? 10.5 (dual/quad) ? 7.8 (serial) ? 9 (dual/quad) ? ns t ho output hold time 0 ?? ns t dis output disable time ?? 8n s t hlch hold# active setup time (relative to sck) 3 ?? ns t chhh hold# active hold time (relative to sck) 3 ?? ns t hhch hold# non active setup ti me (relative to sck) 3 ?? ns t chhl hold# non active hold time (relative to sck) 3 ?? ns t hz hold# enable to output invalid ?? 8n s t lz hold# disable to output valid ?? 8n s t wps w#/acc setup time (4) 20 ?? ns t wph w#/acc hold time (4) 100 ?? ns t w wrr cycle time ?? 50 ms t pp page programming (1)(2) ? 1.5 3 ms t ep page programming (acc = 9v) (1)(2)(3) ? 1.2 2.4 ms t se sector erase time (64 kb) (1)(2) ? 0.5 2 sec sector erase time (256 kb) (1)(2) ? 2 8 sec t be bulk erase time (1)(2)(8) ? 128 256 sec t pe parameter sector erase time (4 kb or 8 kb) (1)(2) ? 200 800 ms t res deep power-down to standby mode ?? 30 s t dp time to enter deep power-down mode ?? 10 s t vhh acc voltage rise and fall time 2.2 ?? s t wc acc at v hh and v il or v ih to first command 5 ??? not recommended for new design
document number: 002-00647 rev. *f page 10 of 16 S70FL256P 4. only applicable as a constraint for wrr instruction when srwd is set to a ?1?. 5. t wh + t wl must be less than or equal to 1/f c . 6. ? full vcc range (2.7 ? 3.6v) and cl = 30 pf. 7. ? regulated vcc range (3.0 ? 3.6v) and cl = 30 pf. 8. bulk erase is on a die per die basis, not for the whole device. 9. when switching between die, a minimum time of t cs must be kept between the rising edge of one chip select and the falling edge of the other for operations and data to be valid. 9.1 capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. 3. for more information on pin capacit ance, please consult the ibis models. symbol parameter test co nditions min typ max unit c in input capacitance (applies to cs1#, cs2#, sck, si/io0, so/io1, w#/acc/io2, hold#/io3) v out = 0v ? 10.0 16.0 pf c out output capacitance (applies to si/io0, so/io1, w#/acc/io2, hold#/io3) v in = 0v ? 22.0 30.0 pf not recommended for new design
document number: 002-00647 rev. *f page 11 of 16 S70FL256P 10. ordering information the ordering part number is formed by a valid combination of the following: 10.1 valid combinations table 10.1 lists the valid combinations configurations pl anned to be supported in volume for this device. note: 1. package marking omits the leading ?s70? and speed, package and model number. s70fl 256 p 0x m f i 00 1 packing type (note 1) 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 21 = bga package, uniform 256 kb sectors 20 = bga package, uniform 64 kb sectors 01 = so package, uniform 256 kb sectors 00 = so package, uniform 64 kb sectors temperature range i = industrial (?40c to + 85c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin so package b = 24-ball bga 6 ? 8 mm package, 1.00 mm pitch speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 256 = 256 mbit device family s70fl cypress stacked memory 3.0v-only, serial peripheral interface (spi) flash memory table 10.1 S70FL256P valid combinations table S70FL256P valid combinations package marking base ordering part number speed option package and temperature model number packing type S70FL256P 0x mfi 00 0, 1, 3 70fl256p0xmfi00 01 70fl256p0xmfi01 bhi 20 0, 3 70fl256p0xbhi20 21 70fl256p0xbhi21 not recommended for new design
document number: 002-00647 rev. *f page 12 of 16 S70FL256P 11. physical dimensions 11.1 sl3 016 ? 16-pin wide plastic small outline package (300-mil body width) 3644 \ 16-038.03 rev c \ 02.03.10 (jk) notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. . package sl3016 (inches) sl3016 (mm) jedec ms-013(d)aa ms-013(d)aa symbol min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 a2 0.081 0.104 2.05 2.55 b 0.012 0.020 0.31 0.51 b1 0.011 0.019 0.27 0.48 c 0.008 0.013 0.20 0.33 c1 0.008 0.012 0.20 0.30 d 0.406 bsc 10.30 bsc e 0.406 bsc 10.30 bsc e1 0.295 bsc 7.50 bsc e .050 bsc 1.27 bsc l 0.016 0.050 0.40 1.27 l1 .055 ref 1.40 ref l2 .010 bsc 0.25 bsc n 16 16 h 0.10 0.30 0.25 0.75 0 8 0 8 1 5 15 5 15 2 0 0 not recommended for new design
document number: 002-00647 rev. *f page 13 of 16 S70FL256P 11.2 zsa024 ? 24-ball ball grid array (6 ? 8 mm) package 3645 16-038.86 rev a \ 02.26.10 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package zsa024 jedec n/a d x e 8.00 mm x 6.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 4.00 bsc. matrix footprint e1 4.00 bsc. matrix footprint md 5 matrix size d direction me 5 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter ee 1.00 bsc. ball pitch ed 1.00 bsc ball pitch sd / se 0.00 solder ball placement a1 depopulated solder balls not recommended for new design
document number: 002-00647 rev. *f page 14 of 16 S70FL256P 12. revision history document history page document title: S70FL256P, 256-mbit 3.0v flash document number: 002-00647 rev. ecn no. orig. of change submission date description of change ** ? bwha 03/03/2010 initial release *a ? bwha 03/17/2010 valid combinations: corrected package marking specificat ion from discrete to mcp format read identification (rdid): added section to explain cfi change from fl129p *b ? bwha 06/17/2010 general: changed product description from ?256-mb it cmos 3.0 volt flash memory with 93-mhz spi serial (serial peripheral in terface) multi i/o bus? to ?256-mbit cmos 3.0 volt flash memory with 104-mhz spi serial (serial peripheral interface) multi i/o bus? changed data sheet status from advanced information to preliminary distinctive characteristics: changed normal read clock rate from 36 to 40 mhz changed fast_read maximum clock rate from 93 to 104 mhz changed dual i/o fast_read clock rate from 72 to 80 mhz and effective data rate from18 to 20 mb/s ordering information: changed description for speed characters 0x from 93 to 104 mhz dc characteristics: changed i li (input leakage current) value from 4 to 2 a (max) changed i lo (output leakage current) value from 4 to 2 a (max) changed i cc1 (active power supply current - read) test condition frequencies from 72/93/36 mhz to 80/104/40 mhz changed i cc1 (active power supply current - read) value @ 80 mhz (dual/ quad) from 41.8 to 44 ma (max) changed i cc1 (active power supply current - read) value @ 104 mhz (serial) from 27.5 to 32 ma (max) changed i cc1 (active power supply current - read) value @ 40 mhz (serial) from13.2 to 15 ma (max) changed i cc2 (active power supply current - page program) value from 28.6 to 26 ma (max) changed i cc3 (active power supply current - wrr) value from 16.5 to 15 ma (max) changed i cc4 (active power supply current - se) value from 28.6 to 26 ma (max) changed i cc5 (active power supply current - be) value from 28.6 to 26 ma (max) added note 2, clarifying that bulk erase is on a die per die basis, not for the whole device test conditions: added note clarifying that input rise and fall times are 0-100% not recommended for new design
document number: 002-00647 rev. *f page 15 of 16 S70FL256P *b (cont.) ? bwha 06/17/2010 ac characteristics: changed f r (sck frequency for read/rdid) values from 36/45 to 40/50 mhz (max) changed f c (sck frequency for others) values from 93/72 to 104/80 mhz (max) changed t v (clock low to output valid) values from 9.6/11.4/7.8/9.6 to 9/10.5/ 7.8/9 ns (max) added t be (bulk erase time) added note 8 clarifying that bulk erase is on a die per die basis, not for the whole device added note 9 clarifying that a minimum time of t cs must be kept between the rising edge of one chip select and the falling edge of the other when switching between die for proper device functionality. capacitance: merged c in capacitance values into a single line item merged single i/o, dual i/o, and quad i/o max capacitance values into a single line item added c in / c out (input / output capacitance) values of 6/8 pf (max) added notes clarifying test conditions *c ? bwha 06/24/2011 global: promoted data sheet designation from preliminary to full production *d ? bwha 01/30/2013 capacitance: added ?typical? values column corrected ?max? values for cin / cout (input / output capacitance) *e 4925834 bwha 09/24/2015 updated to cypress template *f 5155743 bwha 03/10/2016 added nrnd note in page 1 specifying the suggested replacement parts. updated general description . document history page (continued) document title: S70FL256P, 256-mbit 3.0v flash document number: 002-00647 rev. ecn no. orig. of change submission date description of change not recommended for new design
S70FL256P document number: 002-00647 rev. *f revised march 10, 2016 page 16 of 16 ? cypress semiconductor corporation 2010-2016. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of an y product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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